1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory having floating gates and a method for fabricating such a nonvolatile semiconductor memory.
2. Description of the Related Art
A method for fabricating a conventional flash memory will be described with reference to FIGS. 1A to 1C, 2A to 2C, and 3A to 3C. FIG. 1A is a plan view illustrating a first step of the fabrication process of a conventional flash memory, and FIGS. 1B and 1C are sectional views taken along lines B--B and C--C of FIG. 1A, respectively. FIG. 2A is a plan view illustrating a second step of the fabrication process of the flash memory, and FIGS. 2B and 2C are sectional views taken along lines B--B and C--C of FIG. 2A, respectively. FIG. 3A is a plan view illustrating a third step of the fabrication process of the flash memory, and FIGS. 3B and 3C are sectional views taken along lines B--B and C--C of FIG. 3A, respectively.
First, referring to FIGS. 1A to 1C, local oxidation of silicon (LOCOS) oxide films 33 are formed on a semiconductor substrate 21 of a memory cell array 500. The portions of the semiconductor substrate 21 which are not covered with the LOCOS oxide films 33 will remain active regions 34.
Referring to FIGS. 2A to 2C, tunnel oxide films 22 are formed on the active regions 34 of the semiconductor substrate 21, and polysilicon films which are to be floating gates 23 are formed on the tunnel oxide films 22 so as to cover the entire active regions 34. The LOCOS oxide films 33 are ten times or more thicker than the tunnel oxide films 22 and are used as isolators. As shown in FIG. 2C, the floating gates 23 are formed so as to overlap the periphery portions of the LOCOS oxide films 33. Thus, the top surface area of each floating gate 23 is larger than the area thereof in contact with the tunnel oxide film 22. This structure makes it possible to obtain a coupling capacitance C.sub.2 between the floating gate and a control gate larger than a coupling capacitance C.sub.1 between the floating gate and the semiconductor substrate without increasing the coupling capacitance C.sub.1.
Next, referring to FIGS. 3A to 3C, ONO (SiO.sub.2 /SiN/SiO.sub.2) films 29 are formed to cover the floating gates 23 and a material for the control gates is deposited on the resultant substrate. A resist having a pattern of the control gates (word lines) is formed on the deposited material. Using this resist pattern as a mask, the material for the control gates and the ONO films 29 are etched to form control gates 30 as well as the floating gates 23. Thereafter, ions are implanted in the semiconductor substrate 21 using the control gates 30 as a mask, to form source diffusion layers 25a and drain diffusion layers 25b.
In the conventional nonvolatile semiconductor memory 500 shown in FIGS. 1A to 1C, 2A to 2B, and 3A to 3C with the above-described structure, in order to reduce the potential difference V.sub.FG between the floating gate 23 and the semiconductor substrate 21, it is necessary to increase the coupling ratio C.sub.2 /C.sub.1, i.e., the ratio of the coupling capacitance C.sub.2 between the floating gate 23 and the control gate 30 to the coupling capacitance C.sub.1 between the floating gate 23 and the semiconductor substrate 21. At this time, when a voltage V.sub.CG is applied to the control gate 30 and 0 V is applied to the semiconductor substrate 21, the potential difference V.sub.FG between the floating gate 23 and the semiconductor substrate 21 is represented by: EQU V.sub.FG =V.sub.CG .multidot.C.sub.2 /(C.sub.1 +C.sub.2).
As described above, the floating gates 23 extend so as to overlap the LOCOS films 33 in order to increase the coupling ratio. This causes a problem of increasing the cell area.
Impurity diffusion layers may be used as isolators in place of the thick insulating films. In such a case, however, the coupling capacitance C.sub.2 between the floating gate and the control gate cannot be made larger than the coupling capacitance C.sub.1 between the floating gate and the semiconductor substrate by overlapping the floating gate with the impurity diffusion layers. It is therefore difficult to increase the coupling ratio in this case, unlike the case where the thick insulating films are used as isolators.